Conference paper
On the dynamic resistance and reliability of phase change memory
B. Rajendran, M.H. Lee, et al.
VLSI Technology 2008
We have successfully demonstrated a novel "pore" phase change memory cell, whose critical dimension (CD) is independent of lithography. Instead, the pore diameter is accurately defined by intentionally creating a "keyhole" with conformai deposition. Fully integrated 256kbit test chips have been fabricated in 180nm CMOS technology. We report SET times of 80ns, RESET currents less than 250μA, and accurate sub-lithographic CDs that can be less than 20% the size of the lithographically-defined diameter.
B. Rajendran, M.H. Lee, et al.
VLSI Technology 2008
Y.H. Shih, J.Y. Wu, et al.
IEDM 2008
B. Rajendran, M. Breitwisch, et al.
VLSI-TSA 2009
T. Nirschl, J.B. Philipp, et al.
IEDM 2007