Leakage engineering enabling PDSOI ring oscillators operating in sub-100pA/μm I_off regime

This work presents hardware demonstration of low power operation of PDSOI CMOS (Ioff down to ∼10pA/μm at Vdd=0.9V, 45nm node) transistors, exhibiting successful operation of low leakage ring oscillators (channel and junction leakage ∼30pA/invertor stage at Vdd=0.9V, 25C with 101 stages, pFET width=1.2μm, nFET width=0.8μm in each stage). The work highlights device and process feasibility study (through an asymmetric source/drain design) of enabling a PDSOI CMOS based low power application platform. ©The Electrochemical Society.