Publications

46 results for Zhibin Ren

A Software-Assisted Peak Current Regulation Scheme to Improve Power-Limited Inference Performance in a 5nm AI SoC
- - Monodeep Kar
  - Joel Silberman
  - et al.
- 2024
- ISSCC 2024
Power-Limited Inference Performance Optimization Using a Software-Assisted Peak Current Regulation Scheme in a 5-nm AI SoC
- - Monodeep Kar
  - Joel Silberman
  - et al.
- 2024
- IEEE Journal of Solid-State Circuits
A 7-nm Four-Core Mixed-Precision AI Chip with 26.2-TFLOPS Hybrid-FP8 Training, 104.9-TOPS INT4 Inference, and Workload-Aware Throttling
- - Sae Kyu Lee
  - Ankur Agrawal
  - et al.
- 2021
- IEEE JSSC
A 7nm 4-Core AI Chip with 25.6TFLOPS Hybrid FP8 Training, 102.4TOPS INT4 Inference and Workload-Aware Throttling
- - Ankur Agrawal
  - Saekyu Lee
  - et al.
- 2021
- ISSCC 2021
High performance 14nm SOI FinFET CMOS technology with 0.0174μm² embedded DRAM and 15 levels of Cu metallization
- - C.-H.C-H. Lin
  - Brian Greene
  - et al.
- 2014
- IEDM 2014
Statistical measurement of random telegraph noise and its impact in scaled-down high-κ/metal-gate MOSFETs
- - H. Miki
  - N. Tega
  - et al.
- 2012
- IEDM 2012
A comparison of short-channel control in planar bulk and fully depleted devices
- - Ramachandran Muralidhar
  - Jin Cai
  - et al.
- 2012
- IEEE Electron Device Letters
Assessment of fully-depleted planar CMOS for low power complex circuit operation
- - Zhibin Ren
  - S. Mehta
  - et al.
- 2011
- IEDM 2011
Understanding short-term BTI behavior through comprehensive observation of gate-voltage dependence of RTN in highly scaled high-κ / metal-gate pFETs
- - Hiroshi Miki
  - M. Yamaoka
  - et al.
- 2011
- VLSI Technology 2011
ETSOI CMOS for system-on-chip applications featuring 22nm gate length, sub-100nm gate pitch, and 0.08μm² SRAM cell
- - Kangguo Cheng
  - A. Khakifirooz
  - et al.
- 2011
- VLSI Circuits 2011