Weichang Lin, Nicholas Polomoff, et al.
ECTC 2026
Abstract—Interconnect technology has emerged as a key bottleneck in continued chip scaling. Hybrid bonding addresses this challenge by enabling high-density integration at sub-10 µm pitches. As interconnect dimensions shrink further, ensuring electrical reliability under high current density becomes increasingly important. Our study investigates microstructure developments of hybrid bonded Cu structures consisting of Cu pads, vias, and lines embedded within dielectric layers under accelerated electromigration conditions. The goal is to link the observed microstructural features with the scalability, reliability, and electrical performance of hybrid bonding. Accordingly, this study presents recent findings on failure mechanisms of Cu/SiO2 hybrid bonding at the chip-to-chip level as interconnect dimensions are scaled down, spanning Cu pad diameters from 4 to 0.8 µm and sub-10 µm pitches. To uncover failure mechanisms, we combined advanced characterization techniques, including field emission scanning electron microscopy (FE-SEM) and three-dimensional focused ion beam (3D-FIB), to enable 3D nanotomography. Ultimately, this study seeks to bridge fundamental materials insights with practical packaging challenges to advance sub-micron pitch interconnects critical for next-generation 3D chip integration.
Weichang Lin, Nicholas Polomoff, et al.
ECTC 2026
Geoffrey Burr, Sidney Tsai, et al.
CICC 2025
Yigit Turan, Xinchen Wang, et al.
ECTC 2026
Olivier Maher, N. Harnack, et al.
DRC 2023