FAULT MODELLING AND SIMULATION OF SCVS CIRCUITS.
Z. Barzilai, V.S. Iyengar, et al.
ICCD 1983
Simple calculations and estimates are not adequate to show the pros and cons of many complex decisions that designers have to face today. Furthermore, most CAD tools either do not encompass the relationship between cost and performance, or are too complex or time-consuming to use in an iterative fashion for such assessments. The authors describe a design automation system that includes a logic synthesis system and a timer to evaluate various design tradeoffs with a relatively short turnaround time to minimize the time required for design iteration. Examples are given to demonstrate the use of the design methodology to determine the benefits and cost of certain design features.
Z. Barzilai, V.S. Iyengar, et al.
ICCD 1983
R.E. Matick
Journal of Applied Physics
John F. Beetem, P. Debefve, et al.
ICCD 1983
Sharon C. Chuang, Tamal Mukherjee, et al.
VLSI Circuits 1990