An experimental system for power/timing optimization of LSI chips
- B.J. Agule
- J.D. Lesser
- et al.
- 1977
- DAC 1977
Publications
Date
Featured collections
Popular topics
3 results for J.D. Lesser
An Experimental Delay Test Generator for LSI Logic
- Jean Davies Lesser
- John J. Shedletsky
- 1980
- IEEE TC
DESIGN METHODOLOGY FOR EVALUATING DESIGN TRADE-OFFS IN A MICROPROCESSOR SYSTEM.
- Sharon C. Chuang
- R.E. Matick
- et al.
- 1983
- ICCD 1983