P.S. Parkinson, K. Settlemyer, et al.
VLSI-TSA 2003
Conference paper
Challenges in FEOL logic device integration for 32 nm technology node and beyond
Abstract
This paper provides a forum for reviewing and discussing new elements and challenges in the front end of line (FEOL) process integration for 32nm logic devices in the following areas: Metal/high-k (MHK) gate stack, mobility enhancement substrate technology with strain engineering. ©The Electrochemical Society.
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