Monolithic silicon photonics at 25 Gb/s
Jason S. Orcutt, Douglas M. Gill, et al.
OFC 2016
For high performance deep sub .08um CMOS technologies, minimizing short channel effect (SCE) can result in significant improvements in nominal device performance. We show that with carefully chosen carbon implants in the NFET extension and halo region, superior halo performance is achievable. This "Super Halo" characteristic[1], results in an improvement in SCE and a subsequent improvement in Idsat. The carbon implants are placed to reduce the transient diffusion of the boron halo (TED) while not extending deep enough to become a dominant source of leakage. The net is an improved device characteristic resulting in an equivalent performance gain of 80uA/um at nominal with the same Ioff at minimum for both bulk CMOS and SOI technologies.
Jason S. Orcutt, Douglas M. Gill, et al.
OFC 2016
Douglas M. Gill, Chi Xiong, et al.
CLEO 2015
Qiqing Ouyang, Min Yang, et al.
VLSI Technology 2005
Douglas M. Gill, Jonathan E. Proesel, et al.
IEEE JSTQE