Alexander Rylyakov, Thomas Zwick
IEEE Journal of Solid-State Circuits
Conference paper
A wide tuning range (1 GHz-to-15 GHz) fractional-N all-digital PLL in 45nm SOI
Abstract
An all static CMOS (45nm SOI) all-digital fractional-N PLL has a wide tuning range (from 0.84 GHz to 13.3 GHz, at 1.0V, 65°C) and supports a broad range of multiplication factors (up to 1,000x) and reference clock speeds (from 2 MHz to 1 GHz). At 125°C the period jitter of the 4.12 GHz clock (206 MHz reference) is 1.1ps rms (11.4ps pp) at 1.3V (52.4mW), and 2.2pg rms, (22.7ps pp) at 0.7V (9.7mW). The area of the PLL is 175μm × 160μm. ©2008 IEEE.
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