The 12-core POWER8™ processor with 7.6 Tb/s IO bandwidth, integrated voltage regulation, and resonant clocking
- Eric J. Fluhr
- Steve Baumgartner
- et al.
- 2015
- IEEE JSSC
Paper
Publications
4 results for George English
A DPLL-based per core variable frequency clock generator for an eight-core POWER7™ microprocessor
- Jose Tierno
- Alexander Rylyakov
- et al.
- 2010
- VLSI Circuits 2010
Conference paperA wide tuning range (1 GHz-to-15 GHz) fractional-N all-digital PLL in 45nm SOI
- Alexander Rylyakov
- Jose Tierno
- et al.
- 2008
- CICC 2008
Conference paperA wide power-supply range (0.5V-to-1.3V) wide tuning range (500 MHz-to-8 GHz) all-static CMOS AD PLL in 65nm SOI
- A. Rylyakov
- J. Tierno
- et al.
- 2007
- ISSCC 2007
Conference paper