Tony Tae-Hyoung Kim, Pong-Fei Lu, et al.
IEEE Transactions on VLSI Systems
A bulk silicon divide-by-two dynamic frequency divider with maximum clock speed of 26.5 GHz has been achieved. The dynamic divider operates from 6.5 GHz to 26.5 GHz. The design is based on n-channel MOSFET's with an effective gate length of 0.1 µm. © 2000, The Institute of Electrical and Electronics Engineers, Inc. All rights reserved.
Tony Tae-Hyoung Kim, Pong-Fei Lu, et al.
IEEE Transactions on VLSI Systems
Chih-Hsiang Ho, Keith A. Jenkins, et al.
IEEE T-ED
Chih-Hsiang Ho, Keith A. Jenkins, et al.
IRPS 2014
Woogeun Rhee, Keith A. Jenkins, et al.
IEEE TCAS-II