HERMES Core - A 14nm CMOS and PCM-based In-Memory Compute Core using an array of 300ps/LSB Linearized CCO-based ADCs and local digital processing
- Riduan Khaddam-Aljameh
- Milos Stanisavljevic
- et al.
- 2021
- VLSI Circuits 2021
Victor Chan
Title
Yield learning & Diag Eng Prof
Bio
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Current / Recent: STSM in Yield / characterization of 2nm Nanosheet Logic; Analog AI hardware and chiplet technologies.
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Working in semiconductor industry over 20 years in IBM.
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Technical leadership in FEOL integration and device teams of CMOS 90 to deep sub-micron in bulk / SOI technologies, innovative and inventive delivery of process technologies from concept to qualification to manufacturing.
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Specialties include semiconductor device & integration in R&D and production, product - customer deployment, technology licensing and technical support. Extensive experience in running lots and characterization of device / inline-metrology / PLY / Health-of-line and yield data. Device, SRAM and product yield learning and improvement through Hands-on data analysis.
Publications
HERMES Core - A 14nm CMOS and PCM-based In-Memory Compute Core using an array of 300ps/LSB Linearized CCO-based ADCs and local digital processing
- R. Khaddam-Aljameh
- M. Stanisavljevic
- et al.
- 2021
- VLSI Technology 2021
Middle of Line (MOL) Process Investigation in Ring Oscillator failure
- Victor Chan
- M. Bergendahl
- et al.
- 2020
- ASMC 2020
Yield learning methodologies and failure isolation in ring oscillator circuit for CMOS technology research
- Victor Chan
- Kangguo Cheng
- et al.
- 2019
- IEEE Trans Semicond Manuf
Gate-Cut-Last in RMG to Enable Gate Extension Scaling and Parasitic Capacitance Reduction
- A. Greene
- Huimei Zhou
- et al.
- 2019
- VLSI Technology 2019
Failure isolation in ring oscillator circuit and defect detection in CMOS technology research
- Victor Chan
- M. Bergendahl
- et al.
- 2019
- ASMC 2019
Ring oscillator yield learning methodologies for CMOS technology research
- Victor Chan
- D. Lea
- et al.
- 2018
- ASMC 2018
FINFET technology featuring high mobility SiGe channel for 10nm and beyond
- Dechao Guo
- G. Karve
- et al.
- 2016
- VLSI Technology 2016
Blanket SMT with in situ N2 plasma treatment on the lang;100〉 wafer for the low-cost low-power technology application
- Jun Yuan
- Victor Chan
- et al.
- 2009
- IEEE Electron Device Letters
A 45nm low power bulk technology featuring carbon co-implantation and laser anneal on 45°-rotated substrate
- J. Yuan
- V. Chan
- et al.
- 2008
- ICSICT 2008
Patents
- US
- 12150393
- US
- 11309221
- US
- 11257716
- US
- 11222820
- US
- 10985076
- US
- 10943990
- US
- 10229984
- US
- 10043744
- US
- 9935174
- US
- 9929250
Top collaborators
VN
Vijay Narayanan
IBM Fellow & StSenior Manager, Materials Innovation for Logic & Chiplets, Analog AI Compute
GB
Geoffrey Burr
Distinguished RSM
IA
Ishtiaq Ahsan
Senior Manager, Yield/ Test & Characterization, IBM Semiconductor Technology Research & Development