65nm CMOS technology for low power applications
- A. Steegen
- R. Mo
- et al.
- 2005
- IEDM 2005
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18 results at IEDM 2005
From DRAM to SRAM with a novel SiGe-based negative differential resistance (NDR) device
- Liang Yue
- Kailash Gopalakrishnan
- et al.
- 2005
- IEDM 2005
Stress memorization in high-performance FDSOI devices with ultra-thin silicon channels and 25nm gate lengths
- D. Singh
- J. Sleight
- et al.
- 2005
- IEDM 2005
SOI 90-nm ring oscillator sub-ps model-hardware correlation and parasitic-aware optimization leading to 1.94-ps switching delay
- Jean-Olivier Plouchart
- Jonghae Kim
- et al.
- 2005
- IEDM 2005
Systematic study of workfunction engineering and scavenging effect using NiSi alloy FUSI metal gates with advanced gate stacks
- Y.-H. Kim
- C. Cabral Jr.
- et al.
- 2005
- IEDM 2005
Fluctuation limits & scaling opportunities for CMOS SRAM cells
- Azeez Bhavnagarwala
- Stephen Kosonocky
- et al.
- 2005
- IEDM 2005
High performance gate first HfSiON dielectric satisfying 45nm node requirements
- M.A. Quevedo-Lopez
- S. Krishnan
- et al.
- 2005
- IEDM 2005
High performance 65 nm SOI technology with enhanced transistor strain and advanced-low-K BEOL
- W.-H. Lee
- A. Waite
- et al.
- 2005
- IEDM 2005
Design of high performance PFETs with strained Si channel and laser anneal
- Z. Luo
- Y.F. Chong
- et al.
- 2005
- IEDM 2005
Carbon nanotube interconnects: Implications for performance, power dissipation and thermal management
- Navin Srivastava
- Rajiv V. Joshi
- et al.
- 2005
- IEDM 2005