TETA: Transistor-level waveform evaluation for timing analysis
- Emrah Acar
- Florentin Dartu
- et al.
- 2002
- IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
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137 results at IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Wire width planning for interconnect performance optimization
- Jason Cong
- Zhigang Pan
- 2002
- IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Interconnect sizing and spacing with consideration of coupling capacitance
- Jason Cong
- Lei He
- et al.
- 2001
- IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Full-wave PEEC time-domain method for the modeling of on-chip interconnects
- Phillip J. Restle
- Albert E. Ruehli
- et al.
- 2001
- IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Activity-driven clock design
- Amir H. Farrahi
- Chunhong Chen
- et al.
- 2001
- IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Interconnect performance estimation models for design planning
- Jason Cong
- Zhigang Pan
- 2001
- IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Critical area computation for missing material defects in VLSI circuits
- E. Papadopoulou
- 2001
- IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Timed circuit verification using TEL structures
- Wendy Belluomini
- Chris J. Myers
- et al.
- 2001
- IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Interconnect synthesis without wire tapering
- Charles J. Alpert
- Anirudh Devgan
- et al.
- 2001
- IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Timed state space exploration using POSET's
- Wendy Belluomini
- Chris J. Myers
- 2000
- IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems