Lerong Cheng, Jinjun Xiong, et al.
ASP-DAC 2008
This paper studies interconnect sizing and spacing (ISS) problem with consideration of coupling capacitance for performance optimization of single or multiple critical nets. We introduce the formulation of symmetric and asymmetric wire sizing. We develop efficient bound computation algorithms for ISS optimization and prove their optimality under general interconnect resistance and capacitance models. Our experiments show that our algorithms are very effective and obtain significant performance improvement compared to previous wire-sizing/spacing algorithms.
Lerong Cheng, Jinjun Xiong, et al.
ASP-DAC 2008
Lerong Cheng, Jinjun Xiong, et al.
DAC 2007
Jinjun Xiong, Vladimir Zolotov, et al.
ISPD 2006
Jason Cong, Tianming Kong, et al.
IEEE Transactions on VLSI Systems