A 28 GHz hybrid PLL in 32 nm SOI CMOS
- Mark Ferriss
- Alexander Rylyakov
- et al.
- 2014
- IEEE JSSC
Paper
Publications
121 results at IEEE JSSC
Highlights of the isscc 2013 processors and high performance digital sessions
- Timothy Fischer
- Byeong-Gyu Nam
- et al.
- 2014
- IEEE JSSC
ReviewA 3.1 mW 8b 1.2 GS/s single-Channel asynchronous SAR ADC with alternate comparators for enhanced speed in 32 nm digital SOI CMOS
- Lukas Kull
- Thomas Toifl
- et al.
- 2013
- IEEE JSSC
PaperA 10 Gb/s 8-tap 6b 2-PAM/4-PAM tomlinson-harashima precoding transmitter for future memory-link applications in 22-nm SOI CMOS
- Marcel Kossel
- Thomas Toifl
- et al.
- 2013
- IEEE JSSC
PaperA linearized, low-phase-noise VCO-based 25-GHz PLL with autonomic biasing
- Bodhisatwa Sadhu
- Mark A. Ferriss
- et al.
- 2013
- IEEE JSSC
PaperAn integral path self-calibration scheme for a dual-loop PLL
- Mark Ferriss
- Jean-Olivier Plouchart
- et al.
- 2013
- IEEE JSSC
PaperA millimeter-scale energy-autonomous sensor system with stacked battery and solar cells
- Matthew Fojtik
- Daeyeon Kim
- et al.
- 2013
- IEEE JSSC
PaperA 2.5D integrated voltage regulator using coupled-magnetic-core inductors on silicon interposer
- Noah Sturcken
- Eugene J. O'Sullivan
- et al.
- 2013
- IEEE JSSC
PaperA 28-Gb/s 4-Tap FFE/15-Tap DFE Serial Link Transceiver in 32-nm SOI CMOS Technology
- John F. Bulzacchelli
- Christian Menolfi
- et al.
- 2012
- IEEE JSSC
PaperA 16-Gb/s backplane transceiver with 12-tap current integrating DFE and dynamic adaptation of voltage offset and timing driftsin 45-nm SOI CMOS technology
- Gautam R. Gangasani
- Chun-Ming Hsu
- et al.
- 2012
- IEEE JSSC
Paper