The NorthPole Validator: A Cycle-Accurate Simulator for HW/SW Codesign of a Prescheduled Neural Inference AcceleratorAlexander AndreopoulosMichael V. Deboleet al.2025HPEC 2025
SSD controller architecture for similarity search in Vector DBsRoman PletkaJovan Blanusaet al.2025FMS 2025
Deep learning software stacks for analogue in-memory computing-based acceleratorsCorey Liam LammieHadjer Benmezianeet al.2025Nat. Rev. Electr. Eng.
Architecture and Design Approaches towards Large-scale AI Hardware AccelerationAshish Ranjan2025DAC 2025
Innovative BEOL Oxide-Based Devices as Key Enablers for High-Performing Heterogeneous SystemsValeria BragagliaWooseok Choiet al.2025DRC 2025
Routing Congestion Mitigation Techniques Targeting Dense DesignsAlex SuessLakshmi Reddyet al.2025DAC 2025
DiReC: Enhancing VHDL Code Generation and Summarization with Divide-Retrieve-Conquer StrategyPrashanth VijayaraghavanApoorva Nitsureet al.2025DAC 2025
A Near-DRAM Accelerator for Compiler-Generated Fully Homomorphic Encryption ApplicationsAlper Buyuktosunoglu2025ISCA 2025
Scalable Physical Design for Many-Accelerator SoCsKarthik SwaminathanMartin Cochetet al.2025ISCA 2025