An integrated methodology for accurate extraction of S/D series resistance components in nanoscale MOSFETsSeong-Dong KimShreesh Narasimhaet al.2005IEDM 2005
Enabling SOI-based assembly technology for three-dimensional (3D) integrated circuits (ICs)A. TopolD.C. La Tulipeet al.2005IEDM 2005
Performance and limitations of 65 nm CMOS for integrated RF power applicationsJörg ScholvinDavid R. Greenberget al.2005IEDM 2005
Carbon nanotube interconnects: Implications for performance, power dissipation and thermal managementNavin SrivastavaRajiv V. Joshiet al.2005IEDM 2005
Design of high performance PFETs with strained Si channel and laser annealZ. LuoY.F. Chonget al.2005IEDM 2005
High performance 65 nm SOI technology with enhanced transistor strain and advanced-low-K BEOLW.-H. LeeA. Waiteet al.2005IEDM 2005
Fluctuation limits & scaling opportunities for CMOS SRAM cellsAzeez BhavnagarwalaStephen Kosonockyet al.2005IEDM 2005