Assessment of fully-depleted planar CMOS for low power complex circuit operationZhibin RenS. Mehtaet al.2011IEDM 2011
The impact of hole-induced electromigration on the cycling endurance of phase change memoryM. H. LeeR. Cheeket al.2010IEDM 2010
Hysteretic drain-current behavior due to random telegraph noise in scaled-down FETs with high-κ/metal-gate stacksHiroshi MikiNaoki Tegaet al.2010IEDM 2010
Challenges and solutions of FinFET integration in an SRAM cell and a logic circuit for 22 nm node and beyondH. KawasakiV.S. Baskeret al.2009IEDM 2009
Reduction of random telegraph noise in high-κ / metal-gate stacks for 22 nm generation FETsN. TegaH. Mikiet al.2009IEDM 2009
Extremely thin SOI (ETSOI) CMOS with record low variability for low power system-on-chip applicationsK. ChengA. Khakifiroozet al.2009IEDM 2009
Understanding amorphous states of phase-change memory using frenkel-poole modelY.H. ShihM.H. Leeet al.2009IEDM 2009
Mechanisms of retention loss in Ge2Sb2Te 5-based phase-change memoryY.H. ShihJ.Y. Wuet al.2008IEDM 2008
22 nm technology compatible fully functional 0.1 μm 2 6T-sram cellB. HaranA. Kumaret al.2008IEDM 2008
Write strategies for 2 and 4-bit multi-level phase-change memoryT. NirschlJ.B. Philippet al.2007IEDM 2007