A high-performance 0.5-μm BiCMOS technology with 3.3-V CMOS devices
- Eric D. Johnson
- T.B. Hook
- et al.
- 1990
- VLSI Technology 1990
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58 results for Terence B. Hook
Advanced FDSOI Device Design: The U-Channel Device for 7 nm Node and beyond
- Ramachandran Muralidhar
- Robert Dennard
- et al.
- 2018
- IEEE J-EDS
Impact of hot-carrier degradation on drain-induced barrier lowering in multifin SOI n-Channel FinFETs with self-heating
- Charu Gupta
- Anshul Gupta
- et al.
- 2020
- IEEE T-ED
Reliability Modeling and Analysis of Hot-Carrier Degradation in Multiple-Fin SOI n-Channel FinFETs With Self-Heating
- Anshul Gupta
- Charu Gupta
- et al.
- 2019
- IEEE T-ED
Modeling of Effective Thermal Resistance in Sub-14-nm Stacked Nanowire and FinFETs
- Ishita Jain
- Anshul Gupta
- et al.
- 2018
- IEEE T-ED
OFF-State Leakage and Performance Variations Associated with Germanium Preamorphization Implant in Silicon-Germanium Channel pFET
- Vishal A. Tiwari
- Rama Divakaruni
- et al.
- 2018
- IEEE T-ED
Series Resistance Reduction with Linearity Assessment for Vertically Stacked Junctionless Accumulation Mode Nanowire FET
- Anil K. Bansal
- Manoj Kumar
- et al.
- 2018
- IEEE T-ED
3-D LER and RDF Matching Performance of Nanowire FETs in Inversion, Accumulation, and Junctionless Modes
- Anil K. Bansal
- Charu Gupta
- et al.
- 2018
- IEEE T-ED
Analytical Modeling of Parasitic Capacitance in Inserted-Oxide FinFETs
- R. Singh
- Anshul Gupta
- et al.
- 2017
- IEEE T-ED
Series resistance reduction in stacked nanowire FETs for 7-nm CMOS technology
- Anil K. Bansal
- Ishita Jain
- et al.
- 2016
- IEEE J-EDS