ETSOI CMOS for system-on-chip applications featuring 22nm gate length, sub-100nm gate pitch, and 0.08μm2 SRAM cell
- Kangguo Cheng
- A. Khakifirooz
- et al.
- 2011
- VLSI Circuits 2011
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58 results for Terence B. Hook
Impact of back bias on ultra-thin body and BOX (UTBB) devices
- Q. Liu
- Frederic Monsieur
- et al.
- 2011
- VLSI Technology 2011
Ultra-thin Body and BOX (UTBB) device for aggressive scaling of CMOS technology
- Q. Liu
- A. Yagishita
- et al.
- 2011
- CSTIC 2011
Reduction of RTA-driven intra-die variation via model-based layout optimization
- J.C. Scott
- O. Gluschenkov
- et al.
- 2009
- VLSI Technology 2009
SOI antennas and wafer bulk connection
- Terence B. Hook
- Mario M. Pelella
- 2008
- IEEE International SOI Conference 2008
Characterization and analysis of gate-induced-drain-leakage current in 45 nm CMOS technology
- Xiaobin Yuan
- Jae-Eun Park
- et al.
- 2007
- IIRW 2007
A 45nm low cost low power platform by using integrated dual-stress-liner technology
- J. Yuan
- S.S. Tan
- et al.
- 2006
- VLSI Technology 2006
Evaluation of device damage from e-beam curing of ultra low-k BEOL dielectrics
- S. Mehta
- C. Dimitrakopoulos
- et al.
- 2005
- AMC 2005
Interface state generation in pFETs with ultra-thin oxide and oxynitride on (100) and (110) Si substrates
- J.H. Stathis
- R. Bolam
- et al.
- 2005
- INFOS 2005
Enhanced multi-threshold (MTCMOS) circuits using variable well bias
- S.V. Kosonocky
- M.J. Immediato
- et al.
- 2001
- ISLPED 2001