Publications

50 results for B. Davari

Workload and network-optimized computing systems
- - D.P. LaPotin
  - Shahrokh Daijavad
  - et al.
- 2010
- IBM J. Res. Dev
1GHz fully pipelined 3.7ns Address access time 8kx1024 embedded DRAM macro
- - O. Takahashi
  - S. Dhong
  - et al.
- 2000
- ISSCC 2000
1-GHz fully pipelined 3.7-ns address access time 8 k × 1024 embedded synchronous DRAM macro
- - Osamu Takahashi
  - Sang H. Dhong
  - et al.
- 2000
- IEEE Journal of Solid-State Circuits
0.22 μm CMOS-SOI technology with a Cu BEOL
- - A. Ajmera
  - J. Sleight
  - et al.
- 1999
- VLSI Technology 1999
Device and circuit design issues in SOI technology
- - G. Shahidi
  - A. Ajmera
  - et al.
- 1999
- CICC 1999
Scalability of SOI technology into 0.13 μm 1.2 V CMOS generation
- - E. Leobandung
  - M. Sherony
  - et al.
- 1998
- IEDM 1998
Trade-offs in the integration of high performance devices with trench capacitor DRAM
- - S.W. Crowder
  - S. Stiffler
  - et al.
- 1997
- IEDM 1997
7.9/5.5 psec room/low temperature SOI CMOS
- - F. Assaderaghi
  - W. Rausch
  - et al.
- 1997
- IEDM 1997
Transient pass-transistor leakage current in SOI MOSFET's
- - F. Assaderaghi
  - G. Shahidi
  - et al.
- 1997
- IEEE Electron Device Letters
A High-Density 6.9 sq. pm Embedded SRAM Cell in a High-Performance 0.25 μm-Generation CMOS Logic Technology
- - S. Subbanna
  - P. Agnello
  - et al.
- 1996
- IEDM 1996