A 4R2W register file for a 2.3GHz wire-speed POWER™ processor with double-pumped write operation
- Gary S. Ditlow
- Robert K. Montoye
- et al.
- 2011
- ISSCC 2011
Conference paper
Publications
6 results for Shohji Onishi
Microarchitecture and implementation of the synergistic processor in 65-nm and 90-nm SOI
- Brian Flachs
- Shigehiro Asano
- et al.
- 2007
- IBM J. Res. Dev
PaperThe circuits and physical design of the synergistic processor element of a CELL processor
- O. Takahashi
- R. Cook
- et al.
- 2005
- VLSI Circuits 2005
Conference paperThe circuit design of the synergistic processor element of a CELL processor
- O. Takahashi
- R. Cook
- et al.
- 2005
- ICCAD 2005
Conference paper1GHz fully pipelined 3.7ns Address access time 8kx1024 embedded DRAM macro
- O. Takahashi
- S. Dhong
- et al.
- 2000
- ISSCC 2000
Conference paper1-GHz fully pipelined 3.7-ns address access time 8 k × 1024 embedded synchronous DRAM macro
- Osamu Takahashi
- Sang H. Dhong
- et al.
- 2000
- IEEE Journal of Solid-State Circuits
Paper