Publications

13 results for John Barth

Isolated Preset Architecture for a 32nm SOI embedded DRAM macro
- - John Barth
  - Don Plass
  - et al.
- 2012
- VLSI Circuits 2012
Performance analysis and modeling of deep trench decoupling capacitor for 32 nm high-performance SOI processors and beyond
- - Balaji Jayaraman
  - Sneha Gupta
  - et al.
- 2012
- ICICDT 2012
IBM POWER7 processor circuit design
- - Dieter Wendel
  - John Barth
  - et al.
- 2011
- IBM J. Res. Dev
A 45 nm SOI embedded DRAM macro for the POWER™ processor 32 MByte on-chip L3 cache
- - John Barth
  - Don Plass
  - et al.
- 2011
- IEEE Journal of Solid-State Circuits
A 0.039um² high performance eDRAM cell based on 32nm high-K/metal SOI technology
- - Nauman Z. Butt
  - Kevin McStay
  - et al.
- 2010
- IEDM 2010
Process-design considerations for three dimensional memory integration
- - S.S. Iyer
  - T. Kirihata
  - et al.
- 2009
- VLSI Technology 2009
A 1 MB cache subsystem prototype with 1.8 ns embedded DRAMs in 45 nm SOI CMOS
- - Peter J. Klim
  - John Barth
  - et al.
- 2009
- IEEE Journal of Solid-State Circuits
An on-chip dual supply charge pump system for 45nm PD SOI eDRAM
- - J.B. Kuang
  - A. Mathews
  - et al.
- 2008
- ESSCIRC 2008
A one MB cache subsystem prototype with 2GHz embedded DRAMs in 45nm SOI CMOS
- - Peter Klim
  - John Barth
  - et al.
- 2008
- VLSI Circuits 2008
A 500 MHz Random Cycle, 1.5 ns Latency, SOI Embedded DRAM Macro Featuring a Three-Transistor Micro Sense Amplifier
- - John Barth
  - William R. Reohr
  - et al.
- 2008
- IEEE Journal of Solid-State Circuits