Extremely thin SOI (ETSOI) CMOS with record low variability for low power system-on-chip applications
- K. Cheng
- A. Khakifirooz
- et al.
- 2009
- IEDM 2009
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15 results for Dave Horak
22 nm technology compatible fully functional 0.1 μm 2 6T-sram cell
- B. Haran
- A. Kumar
- et al.
- 2008
- IEDM 2008
56 nm pitch copper dual-damascene interconnects with triple pitch split metal and double pitch split via
- James Hsueh-Chung Chen
- Christopher Waskiewicz
- et al.
- 2012
- IITC 2012
Full metal gate with borderless contact for 14 nm and beyond
- Soon-Cheon Seo
- L.F. Edge
- et al.
- 2011
- VLSI Technology 2011
64 nm pitch Cu dual-damascene interconnects using pitch split double exposure patterning scheme
- Shyng-Tsong Chen
- Hideyuki Tomizawa
- et al.
- 2011
- IITC/MAM 2011
Plasma etch challenges for porous low k materials for 32nm and beyond
- Catherine Labelle
- R. Srivastava
- et al.
- 2011
- CSTIC 2011
Challenges and opportunities of extremely thin SOI (ETSOI) CMOS technology for future low power and general purpose system-on-chip applications
- A. Khakifirooz
- Kangguo Cheng
- et al.
- 2010
- VLSI-TSA 2010
Fabrication of dual damascene BEOL structures using a multi-level multiple exposure (MLME) scheme - Part 2. RIE-based pattern transfer and completion of dual damascene process yielding an electrically functional via chain
- Stefan Harrer
- John C Arnold
- et al.
- 2010
- Proceedings of SPIE - The International Society for Optical Engineering 2010
Copper contact metallization using Ru-based barrier liners for 45 nm and 32 nm nodes: Reliability and device performance
- Soon-Cheon Seo
- Chih-Chao Yang
- et al.
- 2008
- ADMETA 2008
Porous low-k material etch for 32 nm and beyond
- Catherine Labelle
- John Arnold
- et al.
- 2008
- ADMETA 2008