Copper through silicon via (TSV) for 3D integration
- C. Kothandaraman
- B. Himmel
- et al.
- 2012
- IRPS 2012
Conference paper
Publications
8 results for K. Petrarca
3D copper TSV integration, testing and reliability
- Mukta Farooq
- T. Graves-Abe
- et al.
- 2011
- IEDM 2011
Conference paperA 45 nm CMOS node Cu/low-k/ ULtra low-k PECVD SiCOH (k=2.4) BEOL technology
- S. Sankaran
- S. Arai
- et al.
- 2006
- IEDM 2006
Conference paperA SiCOH BEOL interconnect technology for high density and high performance 65 nm CMOS applications
- Matthew Angyal
- Jason Gill
- et al.
- 2005
- AMC 2005
Conference paperAsh-induced modification of porous and dense SiCOH inter-level-dielectric (ILD) materials during damascene plasma processing
- T. Dalton
- N. Fuller
- et al.
- 2004
- IITC 2004
Conference paperTwo gates are better than one
- P. Solomon
- K.W. Guarini
- et al.
- 2003
- IEEE Circuits and Devices Magazine
PaperCharacteristics and device design of sub-100 nm strained Si N- and PMOSFETs
- K. Rim
- J.O. Chu
- et al.
- 2002
- VLSI Technology 2002
Conference paperTriple-self-aligned, planar double-gate MOSFETs: Devices and circuits
- K.W. Guarini
- P. Solomon
- et al.
- 2001
- Technical Digest-International Electron Devices Meeting
Paper