Publications

29 results for Pranita Kulkarni

Strain engineered extremely thin SOI (ETSOI) for high-performance CMOS
- - A. Khakifirooz
  - Kangguo Cheng
  - et al.
- 2012
- VLSI Technology 2012
A comparison of short-channel control in planar bulk and fully depleted devices
- - Ramachandran Muralidhar
  - Jin Cai
  - et al.
- 2012
- IEEE Electron Device Letters
Scalability of extremely thin SOI (ETSOI) MOSFETs to sub-20-nm gate length
- - Ali Khakifirooz
  - Kangguo Cheng
  - et al.
- 2012
- IEEE Electron Device Letters
Analysis of parasitic resistance in double gate FinFETs with different fin lengths
- - X. Yang
  - Kingsuk Maitra
  - et al.
- 2011
- IEEE International SOI Conference 2011
Assessment of fully-depleted planar CMOS for low power complex circuit operation
- - Zhibin Ren
  - S. Mehta
  - et al.
- 2011
- IEDM 2011
Impact of substrate bias on GIDL for thin-BOX ETSOI devices
- - Pranita Kulkarni
  - Q. Liu
  - et al.
- 2011
- SISPAD 2011
Critical analysis of 14nm device options
- - Phil Oldiges
  - R. Muralidhar
  - et al.
- 2011
- SISPAD 2011
Impact of back bias on ultra-thin body and BOX (UTBB) devices
- - Q. Liu
  - Frederic Monsieur
  - et al.
- 2011
- VLSI Technology 2011
Sub-25nm FinFET with advanced fin formation and short channel effect engineering
- - Tenko Yamashita
  - Veeraraghvan S. Basker
  - et al.
- 2011
- VLSI Technology 2011
ETSOI CMOS for system-on-chip applications featuring 22nm gate length, sub-100nm gate pitch, and 0.08μm² SRAM cell
- - Kangguo Cheng
  - A. Khakifirooz
  - et al.
- 2011
- VLSI Circuits 2011