A self-aligned silicide process utilizing ion implants for reduced silicon consumption and control of the silicide formation temperature
- G.M. Cohen
- C. Cabral Jr.
- et al.
- 2002
- MRS Proceedings 2002
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81 results for Kevin Chan
Investigations of silicon nano-crystal floating gate memories
- Arvind Kumar
- Jeffrey J. Welser
- et al.
- 2000
- MRS Spring 2000
A self-aligned silicide process for thin silicon-on-insulator MOSFETs and bulk MOSFETs with shallow junctions
- G.M. Cohen
- C. Cabral Jr.
- et al.
- 2001
- MRS Proceedings 2001
Thermal stability of strained Si on relaxed Si1-xGex buffer layers
- P.M. Mooney
- S.J. Koester
- et al.
- 2001
- MRS Proceedings 2001
New polysilicon disposable sidewall process for sub-50 nm CMOS
- K.L. Lee
- D. Boyd
- et al.
- 2001
- ESSDERC 2001
Preparation of 200 mm silicon substrates with metal ground-plane for double-gate SOI devices
- L.J. Huang
- K.K. Chan
- et al.
- 2000
- IEEE International SOI Conference 2000
Bonding of thin films on 200 mm silicon wafers using chemical mechanical polishing
- E.C. Jones
- S. Tiwari
- et al.
- 1998
- IEEE International SOI Conference 1998
Ultra-thin, highly uniform thin film SOI MOSFET with low series resistance using pattern-constrained epitaxy (PACE)
- H.-S. Wong
- K.K. Chan
- et al.
- 1996
- VLSI Technology 1996
Low power 77 K nano-memory with single electron nano-crystal storage
- S. Tiwari
- F. Rana
- et al.
- 1995
- DRC 1995
SiGe-base PNP transistors fabricated with N-type UHV/CVD LTE in a 'No Dt' process
- D.L. Harame
- J.M.C. Stork
- et al.
- 1990
- VLSI Technology 1990