Integration of a manufacturing grade, k = 2.0 spin-on material in a single damascene structure
- Willi Volksen
- Sampath Purushothaman
- et al.
- 2012
- ECS J. Solid State Sci. Technol.
Paper
Publications
30 results for James P. Doyle
A 300-mm wafer-level three-dimensional integration scheme using tungsten through-silicon via and hybrid cu-adhesive bonding
- F. Liu
- R.R. Yu
- et al.
- 2008
- IEDM 2008
Conference paperChip package interaction in ultra low-k/copper interconnect technology
- X.-H. Liu
- T.M. Shaw
- et al.
- 2007
- ICEPT 2007
Conference paperExperimental determination of the toughness of crack stop structures
- T.M. Shaw
- E. Liniger
- et al.
- 2007
- IITC 2007
Conference paperEffect of radical species density and ion bombardment during ashing of extreme ultralow- κ interlevel dielectric materials
- M.A. Worsley
- S. Bent
- et al.
- 2007
- Journal of Applied Physics
PaperA 45 nm CMOS node Cu/low-k/ ULtra low-k PECVD SiCOH (k=2.4) BEOL technology
- S. Sankaran
- S. Arai
- et al.
- 2006
- IEDM 2006
Conference paperThermal stress evolution in embedded Cu/low-k dielectric composite features
- Conal E. Murray
- Charles C. Goldsmith
- et al.
- 2006
- Applied Physics Letters
PaperHybrid lithography: The marriage between optical and e-beam lithography. A method to study process integration and device performance for advanced device nodes
- Steven Steen
- Sharee J. McNab
- et al.
- 2006
- Microelectronic Engineering
PaperBEOL interconnects for 45 nm node and beyond
- R.R. Yu
- J. Doyle
- et al.
- 2005
- VMIC 2005
Conference paperMetal-organic atomic layer deposition of metals for applications in interconnect technology
- O. Van Der Straten
- S.M. Rossnagel
- et al.
- 2005
- ECS Meeting 2005
Conference paper