25 nm CMOS design considerations
- Y. Taur
- C. Wann
- et al.
- 1998
- IEDM 1998
Conference paper
Publications
83 results for Yuan Taur
Generalized scale length for two-dimensional effects in MOSFET's
- David J. Frank
- Yuan Taur
- et al.
- 1998
- IEEE Electron Device Letters
Paper1.0-V and 1.5-V operation of 4-GHz tuned amplifiers implemented in a 0.1-μm CMOS technology on bulk and SOI substrates
- Yo-Chuol Ho
- C. Wann
- et al.
- 1998
- SiRF 1998
Conference paperRF perspective of sub-tenth-micron CMOS
- C. Wann
- L. Su
- et al.
- 1998
- ISSCC 1998
Conference paperDiscrete random dopant distribution effects in nanometer-scale MOSFETs
- Hon-Sum Philip Wong
- Yuan Taur
- et al.
- 1998
- Microelectronics Reliability
PaperFEOL technology trend
- Yuan Taur
- Tak H. Ning
- 1998
- Materials Chemistry and Physics
ReviewHigh-performance 0.07-μm CMOS with 9.5-ps gate delay and 150 GHz fT
- Clement Wann
- Fariborz Assaderaghi
- et al.
- 1997
- IEEE Electron Device Letters
PaperSelf-aligned (top and bottom) double-gate MOSFET with a 25 nm thick silicon channel
- H.-S. Wong
- K.K. Chan
- et al.
- 1997
- IEDM 1997
Conference paperAsymmetry in effective-channel length of n- and p-MOSFETs
- L.R. Logan
- Y. Taur
- et al.
- 1997
- SISPAD 1997
Conference paperModeling and characterization of n+- and p+-polysilicon-gated ultra-thin oxides (21-26 angstroms)
- S.H. Lo
- D.A. Buchanan
- et al.
- 1997
- VLSI Technology 1997
Conference paper