Strained-silicon / silicon-germanium-on-insulator for high-performance CMOS : A manufacturable process for 300 mm substrates
- A. Reznicek
- S.W. Bedell
- et al.
- 2004
- ECS Meeting 2004
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188 results for Devendra Sadana
A hydrogen pre-bake process for Si epitaxy on sige surface
- H. Chen
- S.W. Bedell
- et al.
- 2004
- ECS Meeting 2004
A survey of defects in strained Si layers
- S.W. Bedell
- H. Chen
- et al.
- 2004
- MRS Proceedings 2004
A patterned SOI by masked anneal for system-on-chip applications
- G.M. Cohen
- D.K. Sadana
- 2001
- MRS Proceedings 2001
0.22 μm CMOS-SOI technology with a Cu BEOL
- A. Ajmera
- J. Sleight
- et al.
- 1999
- VLSI Technology 1999
Device and circuit design issues in SOI technology
- G. Shahidi
- A. Ajmera
- et al.
- 1999
- CICC 1999
History dependence of non-fully depleted (NFD) digital SOI circuits
- F. Assaderaghi
- G. Shahidi
- et al.
- 1996
- VLSI Technology 1996
Suppression of the SOI floating-body effects by linked-body device structure
- W. Chen
- Y. Taur
- et al.
- 1996
- VLSI Technology 1996
0.25μm low power CMOS devices and circuits from 8 inch SOI materials
- B. Chen
- A.S. Yapsir
- et al.
- 1995
- ICSICT 1995
Material development of SIMOX with a thin box
- D.K. Sadana
- H.J. Hovel
- et al.
- 1993
- IEEE International SOI Conference 1993