Advanced BEOL Materials, Processes, and Integration to Reduce Line Resistance of Damascene Cu, Co, and Subtractive Ru Interconnects
- Takeshi Nogami
- Oleg Gluschenkov
- et al.
- 2022
- VLSI Technology and Circuits 2022
Publications
23 results for Raghuveer Patlolla
First Experimental Demonstration of MRAM Data Scrubbing: 80 Mb MRAM with 40 nm junctions for Last Level Cache Applications
- H. Wu
- V. Katragadda
- et al.
- 2021
- IEDM 2021
A 14 nm embedded STT-MRAM CMOS technology
- Daniel C. Edelstein
- M. Rizzolo
- et al.
- 2020
- IEDM 2020
Technology challenges and enablers to extend Cu metallization to beyond 7 nm node
- Takeshi Nogami
- H. Huang
- et al.
- 2019
- VLSI Technology 2019
Process Challenges in Fully Aligned Via Integration for sub 32 nm Pitch BEOL
- Benjamin D. Briggs
- C.B. Pcethala
- et al.
- 2018
- IITC 2018
CMP development for Ru liner structures beyond 14nm
- Raghuveer Patlolla
- Koichi Motoyama
- et al.
- 2018
- ECS J. Solid State Sci. Technol.
Future on-chip interconnect metallization and electromigration
- C. K. Hu
- James Kelly
- et al.
- 2018
- IRPS 2018
Fully aligned via integration for extendibility of interconnects to beyond the 7 nm node
- Benjamin D. Briggs
- C.B. Peethala
- et al.
- 2017
- IEDM 2017
Comparison of key fine-line BEOL metallization schemes for beyond 7 nm node
- Takeshi Nogami
- X. Zhang
- et al.
- 2017
- VLSI Technology 2017
Cobalt/copper composite interconnects for line resistance reduction in both fine and wide lines
- Takeshi Nogami
- Raghuveer Patlolla
- et al.
- 2017
- IITC 2017