Towards a viable TDDB reliability assessment methodology: From breakdown physics to circuit failure
- Ernest Y. Wu
- Jordi Suné
- 2009
- IPFA 2009
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62 results for Ernest Y. Wu
High performance 32nm SOI CMOS with high-k/metal gate and 0.149μm 2 SRAM and ultra low-k back end with eleven levels of copper
- B. Greene
- Q. Liang
- et al.
- 2009
- VLSI Technology 2009
Critical Assessment of Soft Breakdown Stability Time and the Implementation of New Post-Breakdown Methodology for ultra-thin gate oxides
- E. Wu
- J. Suñé
- et al.
- 2003
- IEDM 2003
A high performance 90 nm SOI technology with 0.992 μm2 6T-SRAM cell
- Mukesh Khare
- S. Ku
- et al.
- 2002
- IEDM 2002
Electrostatic discharge induced oxide breakdown characterization in a 0.1 μm CMOS technology
- A. Salman
- R. Gauthier
- et al.
- 2002
- IRPS 2002
The effect of change of voltage acceleration on temperature activation of oxide breakdown for ultrathin oxides
- E. Wu
- J.M. McKenna
- et al.
- 2001
- IEEE Electron Device Letters
Breakdown measurements of ultra-thin SiO2 at low voltage
- J.H. Stathis
- A. Vayshenker
- et al.
- 2000
- VLSI Technology 2000
Ultra-thin oxide reliability for ULSI applications
- Ernest Y. Wu
- James H. Stathis
- et al.
- 2000
- Semiconductor Science and Technology
Gate oxide breakdown under Current Limited Constant Voltage Stress
- B.P. Linder
- J.H. Stathis
- et al.
- 2000
- Digest of Technical Papers-Symposium on VLSI Technology
Challenges for accurate reliability projections in the ultra-thin oxide regime
- E. Wu
- W.W. Abadeer
- et al.
- 1999
- IRPS 1999