Novel Advanced Low-k Dielectric for 2 nm and Beyond Cu and Post Cu Dual Damascene BEOL Interconnect Technologies
- Son Nguyen
- Huai Huang
- et al.
- 2025
- VLSI Technology and Circuits 2025
Publications
24 results for Kisik Choi
Fully subtractive Ru Topvia interconnects with minimum 9 nm-space airgap for RC performance and reliability enhancement as post-Cu interconnects
- Koichi Motoyama
- Jaemyung Choi
- et al.
- 2024
- IEDM 2024
Backside power distribution for nanosheet technologies beyond 2nm
- Ruilong Xie
- Wonhyuk Hong
- et al.
- 2024
- VLSI Technology and Circuits 2024
A novel single damascene process for via metal corrosion-free interconnects in advanced nodes
- Koichi Motoyama
- Dominik Metzler
- et al.
- 2024
- IITC 2024
EUV Double Patterning Solution for Subtractive Metal Patterning at 18nm Pitch
- Chris Penny
- Koichi Motoyama
- et al.
- 2024
- SPIE Advanced Lithography + Patterning 2024
A novel integration scheme for self-aligend Ru topvia as post-Cu alternative metal interconnects
- K. Motoyama
- D. Metzler
- et al.
- 2023
- IITC/MAM 2023
Overlay Performance in Permanent Bonded Wafer Integration Schemes
- Nathan Ip
- Michael Belyansky
- et al.
- 2023
- SPIE Advanced Lithography + Patterning 2023
Subtractive Ru Interconnect Enabled by Novel Patterning Solution for EUV Double Patterning and TopVia with Embedded Airgap Integration for Post Cu Interconnect Scaling
- C. J. Penny
- Koichi Motoyama
- et al.
- 2022
- IEDM 2022
BEOL compatible high-capacitance MIMCAP structure using a novel high k material
- P. Jamison
- John Massey
- et al.
- 2020
- IMCS 2020
Exploring the Limits of Cobalt Liner Thickness in Advanced Copper Interconnects
- Nicholas A. Lanzillo
- Kisik Choi
- et al.
- 2019
- IEEE Electron Device Letters