Publications

38 results for N. Zamdmer

High performance 14nm SOI FinFET CMOS technology with 0.0174μm² embedded DRAM and 15 levels of Cu metallization
- - C.-H.C-H. Lin
  - Brian Greene
  - et al.
- 2014
- IEDM 2014
Off-state self-heating, micro-hot-spots, and stress-induced device considerations in scaled technologies
- - Siyu Koswatta
  - N. Mavilla
  - et al.
- 2015
- IEDM 2015
Chip-level power-performance optimization through thermally-driven across-chip variation (ACV) reduction
- - X. Yu
  - Oleg Gluschenkov
  - et al.
- 2011
- IEDM 2011
ETSOI CMOS for system-on-chip applications featuring 22nm gate length, sub-100nm gate pitch, and 0.08μm² SRAM cell
- - Kangguo Cheng
  - A. Khakifirooz
  - et al.
- 2011
- VLSI Technology 2011
ETSOI CMOS for system-on-chip applications featuring 22nm gate length, sub-100nm gate pitch, and 0.08μm² SRAM cell
- - Kangguo Cheng
  - A. Khakifirooz
  - et al.
- 2011
- VLSI Circuits 2011
Reduction of RTA-driven intra-die variation via model-based layout optimization
- - J.C. Scott
  - O. Gluschenkov
  - et al.
- 2009
- VLSI Technology 2009
Improved effective switching current (I_eff+) and capacitance methodology for CMOS circuit performance prediction and model-to-hardware correlation
- - Xiaojun Yu
  - Shu-Jen Han
  - et al.
- 2008
- IEDM 2008
SOI CMOS technology with 360GHz f_T NFET, 260GHz f_T PFET, and record circuit performance for millimeter-wave digital and analog system-on-chip applications
- - Sungjae Lee
  - Jonghae Kim
  - et al.
- 2007
- VLSI Technology 2007
RTA-driven intra-die variations in stage delay, and parametric sensitivities for 65nm technology
- - I. Ahsan
  - N. Zamdmer
  - et al.
- 2006
- VLSI Technology 2006
Modeling of variation in submicrometer CMOS ULSI technologies
- - Scott K. Springer
  - Sungjae Lee
  - et al.
- 2006
- IEEE Transactions on Electron Devices