Manufacturable parasitic-aware circuit-level FETs in 65-nm SOI CMOS technology
- Daeik Kim
- Jonghae Kim
- et al.
- 2007
- IEEE Electron Device Letters
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50 results for Greg Freeman
3.9 ps SiGe HBT ECL ring oscillator and transistor design for minimum gate delay
- Basanth Jagannathan
- Mounir Meghelli
- et al.
- 2003
- IEEE Electron Device Letters
A 4.2-ps ECL ring-oscillator in a 285-GHz f MAX SiGe technology
- Basanth Jagannathan
- Mounir Meghelli
- et al.
- 2002
- IEEE Electron Device Letters
Self-aligned SiGe NPN transistors with 285 GHz f MAX and 207 GHz f T in a manufacturable technology
- B. Jagannathan
- M. Khater
- et al.
- 2002
- IEEE Electron Device Letters
Experimental analysis and modeling of self heating effect in dielectric isolated planar and fin devices
- S. Lee
- Richard A. Wachnik
- et al.
- 2013
- VLSI Technology 2013
Impact of source/drain contact and gate finger spacing on the RF reliability of 45-nm RF nMOSFETs
- Rajan Arora
- Sachin Seth
- et al.
- 2011
- IRPS 2011
Embedded memory considerations in SOI
- G. Wang
- Carl Radens
- et al.
- 2010
- IEEE International SOI Conference 2010
Access transistor design and optimization for 65/45nm high performance SOI eDRAM
- G. Wang
- P. Parries
- et al.
- 2008
- VLSI-TSA 2008
A simple hardware-based statistical model on 65nm SOI CMOS technology
- Q. Liang
- J.B. Johnson
- et al.
- 2007
- ISDRS 2007
SOI CMOS technology with 360GHz fT NFET, 260GHz fT PFET, and record circuit performance for millimeter-wave digital and analog system-on-chip applications
- Sungjae Lee
- Jonghae Kim
- et al.
- 2007
- VLSI Technology 2007