Publications

26 results for X. Chen

A cost effective 32nm high-K/metal gate CMOS technology for low power applications with single-metal/gate-first process
- - X. Chen
  - S. Samavedam
  - et al.
- 2008
- VLSI Technology 2008
Effect of end-of-range defects on device leakage in direct silicon bonded (DSB) technology
- - Haizhou Yin
  - M. Hamaguchi
  - et al.
- 2008
- VLSI-TSA 2008
Scalability of Direct Silicon Bonded (DSB) technology for 32nm node and beyond
- - Haizhou Yin
  - C.Y. Sung
  - et al.
- 2007
- VLSI Technology 2007
CMOS fabricated by hybrid-orientation technology (HOT)
- - Bin Yang
  - M. Yang
  - et al.
- 2007
- IEDST 2007
Direct silicon bonded (DSB) substrate solid phase epitaxy (SPE) integration scheme study for high performance bulk CMOS
- - Haizhou Yin
  - C.Y. Sung
  - et al.
- 2006
- IEDM 2006
Stress proximity technique for performance improvement with dual stress liner at 45nm technology and beyond
- - X. Chen
  - S. Fang
  - et al.
- 2006
- VLSI Technology 2006
High performance 45-nm SOI technology with enhanced strain, porous low-k BEOL, and immersion lithography
- - S. Narasimha
  - K. Onishi
  - et al.
- 2006
- IEDM 2006
Lower resistance scaled metal contacts to silicide for advanced CMOS
- - A. Topol
  - C. Sheraw
  - et al.
- 2006
- VLSI Technology 2006
Process induced stress for CMOS performance improvement
- - S. Fang
  - S.S. Tan
  - et al.
- 2006
- ICSICT 2006
Dual stress liner enhancement in hybrid orientation technology
- - C. Sheraw
  - M. Yang
  - et al.
- 2005
- VLSI Technology 2005