Publications

29 results for A. Bryant

ETSOI CMOS for system-on-chip applications featuring 22nm gate length, sub-100nm gate pitch, and 0.08μm² SRAM cell
- - Kangguo Cheng
  - A. Khakifirooz
  - et al.
- 2011
- VLSI Technology 2011
Opportunities and challenges of FinFET as a device structure candidate for 14nm node CMOS technology
- - Tenko Yamashita
  - Veeraraghvan S. Basker
  - et al.
- 2011
- CSTIC 2011
Non-planar device architecture for 15nm node: FinFET or trigate?
- - Chung-Hsun Lin
  - Josephine Chang
  - et al.
- 2010
- IEEE International SOI Conference 2010
Impact of lateral asymmetric channel doping on 45-nm-technology N-Type SOI MOSFETs
- - Hasan M. Nayfeh
  - Nivo Rovedo
  - et al.
- 2009
- IEEE Transactions on Electron Devices
Trigate 6T SRAM scaling to 0.06 μm²
- - M. Guillorn
  - J. Chang
  - et al.
- 2009
- IEDM 2009
FinFET resistance mitigation through design and process optimization
- - Cindy Wang
  - Josephine Chang
  - et al.
- 2009
- VLSI-TSA 2009
FinFET performance advantage at 22nm: An AC perspective
- - M. Guillorn
  - J. Chang
  - et al.
- 2008
- VLSI Technology 2008
Simulation study of multiple FIN FinFET design for 32nm technology node and beyond
- - Xinlin Wang
  - Andres Bryant
  - et al.
- 2007
- SISPAD 2007
Energy optimality and variability in subthreshold design
- - Scott Hanson
  - Bo Zhai
  - et al.
- 2006
- ISLPED 2006
Silicon CMOS devices beyond scaling
- - Wilfried Haensch
  - Edward J. Nowak
  - et al.
- 2006
- IBM J. Res. Dev