Design and optimization of ESD lateral NPN device in 14nm Fin FET SOI CMOS technology
- You Li
- Rahul Mishra
- et al.
- 2015
- EOS/ESD 2015
Conference paper
Publications
8 results for Rahul Mishra
ESD device performance analysis in a 14nm Fin FET SOI CMOS technology: Fin-based versus planar-based
- Junjun Li
- Robert Gauthier
- et al.
- 2014
- EOS/ESD 2014
Conference paperEffect of embedded-sige eSiGeon ESD TLP and VFTLP characteristics of diode-triggered silicon controlled rectifiers DTSCRs
- Rahul Mishra
- Junjun Li
- et al.
- 2012
- EOS/ESD 2012
Conference paperTechnology scaling effects on the ESD performance of silicide-blocked PMOSFET devices in nanometer bulk CMOS technologies
- Junjun Li
- Rahul Mishra
- et al.
- 2011
- EOS/ESD 2011
Conference paperDegradation of high-κ/metal gate nMOSFETs under ESD-like stress in a 32-nm technology
- Yang Yang
- Robert J. Gauthier
- et al.
- 2011
- IEEE T-DMR
PaperPulsed gate dielectric breakdown in a 32 nm technology under different ESD stress configurations
- Yang Yang
- Robert Gauthier
- et al.
- 2010
- EOS/ESD 2010
Conference paperCharacterization of high-k/metal gate stack breakdown in the time scale of ESD events
- Yang Yang
- James Di Sarro
- et al.
- 2010
- IRPS 2010
Conference paperTechnology scaling of advanced bulk CMOS on-chip ESD protection down to the 32nm node
- Junjun Li
- Kiran Chatty
- et al.
- 2009
- EOS/ESD 2009
Conference paper