Publications

14 results for Carl Radens

High Performance Nanosheet Technology Optimized for 77 K
- - R. Bao
  - L. Qin
  - et al.
- 2023
- IEDM 2023
A universal hardware-driven PVT and layout-aware predictive failure analytics for SRAM
- - Rajiv V. Joshi
  - Sudesh Saroop
  - et al.
- 2016
- IEEE Transactions on VLSI Systems
Super fast physics-based methodology for accurate memory yield prediction
- - Rajiv V. Joshi
  - Keunwoo Kim
  - et al.
- 2015
- IEEE Transactions on VLSI Systems
High performance 14nm SOI FinFET CMOS technology with 0.0174μm² embedded DRAM and 15 levels of Cu metallization
- - C.-H.C-H. Lin
  - Brian Greene
  - et al.
- 2014
- IEDM 2014
Embedded memory considerations in SOI
- - G. Wang
  - Carl Radens
  - et al.
- 2010
- IEEE International SOI Conference 2010
A 45nm low power bulk technology featuring carbon co-implantation and laser anneal on 45°-rotated substrate
- - J. Yuan
  - V. Chan
  - et al.
- 2008
- ICSICT 2008
A sub-600-mV, fluctuation tolerant 65-nm CMOS SRAM array with dynamic cell biasing
- - Azeez J. Bhavnagarwala
  - Stephen Kosonocky
  - et al.
- 2008
- IEEE Journal of Solid-State Circuits
Characterization of Across-device Linewidth Variation (ADLV) for 65 nm logic SRAM using CDSEM and linewidth roughness algorithms
- - W. Chu
  - C. Radens
  - et al.
- 2006
- SPIE Advanced Lithography 2006
Fluctuation limits & scaling opportunities for CMOS SRAM cells
- - Azeez Bhavnagarwala
  - Stephen Kosonocky
  - et al.
- 2005
- IEDM 2005
High performance 65 nm SOI technology with dual stress liner and low capacitance SRAM cell
- - E. Leobandung
  - H. Nayakama
  - et al.
- 2005
- VLSI Technology 2005