Publications

43 results for Robert Polastre

3D Chip stacking with 50 μm pitch lead-free micro-c4 interconnections
- - Joana Maria
  - Bing Dang
  - et al.
- 2011
- ECTC 2011
CMOS compatible thin wafer processing using temporary mechanical wafer, adhesive and laser release of thin chips/wafers for 3D integration
- - Bing Dang
  - Paul Andry
  - et al.
- 2010
- ECTC 2010
Reliability of a 300-mm-compatible 3DI technology based on hybrid Cu-adhesive wafer bonding
- - R.R. Yu
  - F. Liu
  - et al.
- 2009
- VLSI Technology 2009
Reliability testing of through-silicon vias for high-current 3D applications
- - Steven L. Wright
  - Paul S. Andry
  - et al.
- 2008
- ECTC 2008
Characterization of stacked die using die-to-wafer integration for high yield and throughput
- - K. Sakuma
  - P. Andry
  - et al.
- 2008
- ECTC 2008
Comparison of electromigration performance for Pb-free solders and surface finishes with Ni UBM
- - Minhua Lu
  - Paul Lauro
  - et al.
- 2008
- ECTC 2008
3D silicon integration
- - J. Knickerbocker
  - P. Andry
  - et al.
- 2008
- ECTC 2008
3D chip-stacking technology with through-silicon vias and low-volume lead free interconnections
- - Katsuyuki Sakuma
  - Paul S. Andry
  - et al.
- 2008
- IBM J. Res. Dev
3D chip stacking with C4 technology
- - Bing Dang
  - Steven L. Wright
  - et al.
- 2008
- IBM J. Res. Dev
Three-dimensional silicon integration
- - John U. Knickerbocker
  - Paul S. Andry
  - et al.
- 2008
- IBM J. Res. Dev