Publications

19 results for Toke M. Andersen

Modeling and Pareto Optimization of On-Chip Switched Capacitor Converters
- - Toke M. Andersen
  - Florian Krismer
  - et al.
- 2017
- IEEE-TEPL
A 10 W On-Chip Switched Capacitor Voltage Regulator with Feedforward Regulation Capability for Granular Microprocessor Power Delivery
- - Toke M. Andersen
  - Florian Krismer
  - et al.
- 2017
- IEEE-TEPL
Implementation of Low-Power 6-8 b 30-90 GS/s Time-Interleaved ADCs With Optimized Input Bandwidth in 32 nm CMOS
- - Lukas Kull
  - J. Pliva
  - et al.
- 2016
- IEEE JSSC
Modeling and multi-objective optimization of 2.5D inductor-based Fully Integrated Voltage Regulators for microprocessor applications
- - Pedro André Martins Bezerra
  - Florian Krismer
  - et al.
- 2015
- COBEP/SPEC 2015
A 3.6pJ/b 56Gb/s 4-PAM receiver with 6-Bit TI-SAR ADC and quarter-rate speculative 2-tap DFE in 32 nm CMOS
- - Hazar Yueksel
  - Lukas Kull
  - et al.
- 2015
- ESSCIRC 2015
A feedforward controlled on-chip switched-capacitor voltage regulator delivering 10W in 32nm SOI CMOS
- - Toke M. Andersen
  - Florian Krismer
  - et al.
- 2015
- ISSCC 2015
A 110 mW 6 bit 36 GS/s interleaved SAR ADC for 100 GBE occupying 0.048 mm² in 32 nm SOI CMOS
- - Lukas Kull
  - J. Pliva
  - et al.
- 2014
- A-SSCC 2014
A 16 Gb/s 3.7 mW/Gb/s 8-tap DFE receiver and baud-rate CDR with 31 kppm tracking bandwidth
- - Pier Andrea Francese
  - Thomas Toifl
  - et al.
- 2014
- IEEE JSSC
A DDR3/4 memory link TX supporting 24-40 ω, 0.8-1.6 V, 0.8-5.0 Gb/s with slew rate control and thin oxide output stages in 22-nm CMOS SOI
- - Marcel Kossel
  - Christian Menolfi
  - et al.
- 2014
- ESSCIRC 2014
A 16 Gb/s receiver with DC wander compensated rail-to-rail AC coupling and passive linear-equalizer in 22 nm CMOS
- - Pier Andrea Francese
  - Thomas Toifl
  - et al.
- 2014
- ESSCIRC 2014