1.5-V single work-function W/WN/n+-poly gate CMOS device design with 110-nm buried-channel PMOS for 90-nm vertical-cell DRAM
- Rajesh Rengarajan
- Boyong He
- et al.
- 2002
- IEEE Electron Device Letters
Publications
12 results for Ravikumar Ramachandran
Aluminum dual damascene metallization for 0.175 μm DRAM generations and beyond
- R.F. Schnabel
- L. Clevenger
- et al.
- 2000
- Microelectronic Engineering