Publications

36 results for Shreesh Narasimha

Experimental analysis and modeling of self heating effect in dielectric isolated planar and fin devices
- - S. Lee
  - Richard A. Wachnik
  - et al.
- 2013
- VLSI Technology 2013
22nm High-performance SOI technology featuring dual-embedded stressors, Epi-Plate High-K deep-trench embedded DRAM and self-aligned Via 15LM BEOL
- - S. Narasimha
  - P. Chang
  - et al.
- 2012
- IEDM 2012
Advanced modeling and optimization of high performance 32nm HKMG SOI CMOS for RF/analog SoC applications
- - Sungjae Lee
  - J. Johnson
  - et al.
- 2012
- VLSI Technology 2012
A manufacturable dual channel (Si and SiGe) high-k metal gate CMOS technology with multiple oxides for high performance and low power applications
- - S. Krishnan
  - U. Kwon
  - et al.
- 2011
- IEDM 2011
A 0.039um² high performance eDRAM cell based on 32nm high-K/metal SOI technology
- - Nauman Z. Butt
  - Kevin McStay
  - et al.
- 2010
- IEDM 2010
Impact of lateral asymmetric channel doping on 45-nm-technology N-Type SOI MOSFETs
- - Hasan M. Nayfeh
  - Nivo Rovedo
  - et al.
- 2009
- IEEE Transactions on Electron Devices
On the systematic analysis of ring-delay performance using statistical behavior model
- - Q. Liang
  - B. Greene
  - et al.
- 2009
- ISDRS 2009
A new method to determine effective lateral doping abruptness and spreading-resistance components in nanoscale MOSFETs
- - Seong-Dong Kim
  - Shreesh Narasimha
  - et al.
- 2008
- IEEE Transactions on Electron Devices
(110) Channel, SiON gate-dielectric PMOS with record high I_on=1 mA/μm through channel stress and source drain external resistance (R _ext) engineering
- - B. Yang
  - A. Waite
  - et al.
- 2007
- IEDM 2007
Hole transport in nanoscale p-type MOSFET SOI devices with high strain
- - H. Nayfeh
  - S.-J. Jeng
  - et al.
- 2007
- DRC 2007