Publications

A DDR3/4 memory link TX supporting 24-40 ω, 0.8-1.6 V, 0.8-5.0 Gb/s with slew rate control and thin oxide output stages in 22-nm CMOS SOI

• • Marcel Kossel
  • Christian Menolfi
  • et al.
• 2014
• ESSCIRC 2014