Publications

66 results for Phillip Restle

PACMAN: Driving nonuniform clock grid loads for low-skew robust clock network
- - Nancy Y. Zhou
  - Phillip Restle
  - et al.
- 2014
- SLIP 2014
The POWER8™ processor: Designed for big data, analytics, and cloud environments
- - Joshua Friedrich
  - Hung Le
  - et al.
- 2014
- ICICDT 2014
Wide-frequency-range resonant clock with on-the-fly mode changing for the POWER8^TM microprocessor
- - Phillip Restle
  - David Shan
  - et al.
- 2014
- ISSCC 2014
POWER8^TM: A 12-core server-class processor in 22nm SOI with 7.6Tb/s off-chip bandwidth
- - Eric J. Fluhr
  - Joshua Friedrich
  - et al.
- 2014
- ISSCC 2014
On-chip circuit for measuring multi-GHz clock signal waveforms
- - Keith A. Jenkins
  - P. Restle
  - et al.
- 2013
- VTS 2013
A shorted global clock design for multi-GHz 3D stacked chips
- - Liang-Teck Pang
  - Phillip J. Restle
  - et al.
- 2012
- VLSI Circuits 2012
Subtractive router for tree-driven-grid clocks
- - Haifeng Qian
  - Phillip J. Restle
  - et al.
- 2012
- IEEE TCADIS
Myth busters: Microprocessor clocking is from Mars, ASICs clocking is from Venus
- - Joseph Kozhaya
  - Phillip Restle
  - et al.
- 2011
- ICCAD 2011
POWER7™, a highly parallel, scalable multi-core high end server processor
- - Dieter F. Wendel
  - Ron Kalla
  - et al.
- 2011
- IEEE Journal of Solid-State Circuits
A resonant global clock distribution for the cell broadband engine processor
- - Steven C. Chan
  - Phillip J. Restle
  - et al.
- 2009
- IEEE Journal of Solid-State Circuits