Publications

10 results for David Hui

Droop mitigation using critical-path sensors and an on-chip distributed power supply estimation engine in the z14™ enterprise processor
- - Christos Vezyrtzis
  - T. Strach
  - et al.
- 2018
- ISSCC 2018
Design Considerations for Reconfigurable Delay Circuit to Emulate System Critical Paths
- - Xiaobin Yuan
  - Pawel Owczarczyk
  - et al.
- 2015
- IEEE Transactions on VLSI Systems
A DPLL-based per core variable frequency clock generator for an eight-core POWER7™ microprocessor
- - Jose Tierno
  - Alexander Rylyakov
  - et al.
- 2010
- VLSI Circuits 2010
Silicon-on-insulator dynamic threshold ESD networks and active clamp circuitry
- - S. Voldman
  - D. Hui
  - et al.
- 2002
- Journal of Electrostatics
IBM eServer z900 high-frequency microprocessor technology, circuits, and design methodology
- - Brian W. Curran
  - Yuen H. Chan
  - et al.
- 2002
- IBM J. Res. Dev
Silicon Germanium heterojunction bipolar transistor ESD power clamps and the Johnson Limit
- - Steven H. Voldman
  - Alan Botula
  - et al.
- 2001
- EOS/ESD 2001
Silicon-on-insulator dynamic threshold ESD networks and active clamp circuitry
- - S. Voldman
  - D. Hui
  - et al.
- 2000
- EOS/ESD 2000
Electrostatic discharge (ESD) protection in silicon-on-insulator (SOI) CMOS technology with aluminum and copper interconnects in advanced microprocessor semiconductor chips
- - S. Voldman
  - D. Hui
  - et al.
- 2000
- Journal of Electrostatics
Electrostatic discharge (ESD) protection in silicon-on-insulator (SOI) CMOS technology with aluminum and copper interconnects in advanced microprocessor semiconductor chips
- - S. Voldman
  - D. Hui
  - et al.
- 1999
- EOS/ESD 1999
Electrostatic discharge protection in silicon-on-insulator technology
- - S. Voldman
  - D. Hui
  - et al.
- 1999
- IEEE International SOI Conference 1999