Block-Level Design Optimization for Sub-100-nm Cell Height Libraries with Stacked Transistor
- Nick Lanzillo
- Jim Mazza
- et al.
- 2025
- IEDM 2025
Conference paper
Publications
69 results for Nick Lanzillo
Half-metallic Fe/MgO superlattice: An ideal candidate for magnetic tunnel junction electrodes
- Nicholas A. Lanzillo
- Sergey Faleev
- et al.
- 2025
- Applied Physics Letters
PaperNanoStack Transistor Architecture for CMOS 7A Node and Beyond
- S. Reboh
- C. Zhang
- et al.
- 2025
- VLSI Technology and Circuits 2025
Conference paperNovel Advanced Low-k Dielectric for 2 nm and Beyond Cu and Post Cu Dual Damascene BEOL Interconnect Technologies
- S. Nguyen
- H. Huang
- et al.
- 2025
- VLSI Technology and Circuits 2025
Conference paperInnovations Enabling the Continued Extendibility of Cu and Post-Cu Damascene BEOL Technologies
- D. Edelstein
- A. Jog
- et al.
- 2025
- IITC 2025
Conference paperFirst Demonstration of 16nm Pitch Subtractive Ru Interconnects for Advanced Technology Nodes
- C. Penny
- K. Motoyama
- et al.
- 2025
- IITC 2025
Conference paperA Perspective on Interconnect Scaling Challenges in the NanoStack Transistor Era AP/DFM: Advanced Patterning/Design for Manufacturing (Design-Technology Co-Optimization)
- Nicholas A. Lanzillo
- Shahrukh Khan
- et al.
- 2025
- ASMC 2025
Conference paperMonolithic Stacked FET with Stepped Channels for Future Logic Technologies
- Chen Zhang
- Seungmin Song
- et al.
- 2024
- IEDM 2024
Conference paperFully subtractive Ru Topvia interconnects with minimum 9 nm-space airgap for RC performance and reliability enhancement as post-Cu interconnects
- Koichi Motoyama
- Jaemyung Choi
- et al.
- 2024
- IEDM 2024
Conference paperThe Extreme Extendibility of Cu and Post-Cu Dual Damascene BEOL Interconnect Technology
- Daniel Edelstein
- Son Nguyen
- et al.
- 2024
- IEDM 2024
Invited talk