Performance assessment of scaled strained-Si channel-on-insulator (SSOI) CMOS
- Keunwoo Kim
- Ching-Te Chuang
- et al.
- 2004
- Solid-State Electronics
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210 results for Rajiv V. Joshi
Power analysis of strained-Si devices/circuits
- Keunwoo Kim
- Rajiv V. Joshi
- et al.
- 2004
- Solid-State Electronics
Turning silicon on its edge
- Edward J. Nowak
- Ingo Aller
- et al.
- 2004
- IEEE Circuits and Devices Magazine
Scaling planar silicon devices
- Ching-Te Chuang
- Kerry Bernstein
- et al.
- 2004
- IEEE Circuits and Devices Magazine
PD/SOI SRAM performance in presence of gate-to-body tunneling current
- Rajiv V. Joshi
- Ching-Te Chuang
- et al.
- 2003
- IEEE Transactions on VLSI Systems
Backend implications for thermal effects in 3d integrated soi structures
- D. Celo
- R.V. Joshi
- et al.
- 2003
- AMC 2003
Simulation of the deposition of BCC metals including anistropic effects using 3D-films
- T. Smy
- R.V. Joshi
- 2003
- AMC 2003
New digital circuit techniques for total standby leakage reduction in nano-scale SOI technology
- Koushik K. Das
- Rajiv V. Joshi
- et al.
- 2003
- ESSCIRC 2003
Three dimensional CMOS devices and integrated circuits
- Meikei Ieong
- Kathryn W. Guarini
- et al.
- 2003
- CICC 2003
Design and CAD Challenges in sub-90nm CMOS Technologies
- Kerry Bernstein
- Ching-Te Chuang
- et al.
- 2003
- ICCAD 2003