J.R. Thompson, Yang Ren Sun, et al.
Physica A: Statistical Mechanics and its Applications
Paper
Power analysis of strained-Si devices/circuits
Abstract
The feasibility of nano-scale strained-Si technologies for low-power applications is studied. Static and dynamic power for strained-Si device is analyzed and compared with conventional bulk-Si technology. Optimum device design points are suggested, and strained-Si CMOS circuits are studied, showing substantially reduced power consumptions. The trade-offs for power and performance in strained-Si devices/circuits are discussed. Further, analysis and low-power design points are applied and extended to strained Si on SOI substrate (SSOI) CMOS technology. © 2004 Elsevier Ltd. All rights reserved.
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